1. Field of the Invention
The present invention relates to an electrically rewritable non-volatile semiconductor storage device.
2. Description of the Related Art
As refinement technologies are pushed to the limit for improving the bit density of non-volatile semiconductor storage devices such as NAND type flash memory, there is increasing demand for lamination of memory cells. As one example, there have been proposed such non-volatile semiconductor storage devices where memory cells are configured with vertical transistors (see, for example, Japanese Patent Laid-Open No. 2007-266143). Lamination-type non-volatile semiconductor storage devices have columnar semiconductor layers, MONOS layers formed to surround the columnar semiconductor layers, and conductive layers formed to surround the MONOS layers.
For planar-type non-volatile semiconductor storage devices, the erase operation is performed by increasing the substrate potential corresponding to a channel to an erase voltage so that electrons are removed from relevant MONOS layers. However, the above-mentioned lamination-type non-volatile semiconductor storage devices should involve columnar semiconductor layers as their channels. Thus, it is inefficient and infeasible to perform the erase operation in the lamination-type non-volatile semiconductor storage devices in the same manner as in the planar-type devices.
Therefore, it is desirable to provide such lamination-type non-volatile semiconductor storage devices in which the erase operation can be performed in an efficient manner.